FIG. 15 shows a configuration of a fractional frequency divider circuit disclosed in Patent Document 1, by way of giving a typical relevant technique of a frequency divider circuit with a frequency division number (frequency division ratio) including a number composed of an integer part and a subdecimal part (fractional number). Referring to FIG. 15, the circuit includes a PLL (phase locked loop) circuit 14 comprising a voltage controlled oscillator (VCO) 13, and a plurality of frequency divider circuits 15a to 15i. The VCO 13 outputs, from its four terminals, four oscillation frequencies, obtained on equal phase division of a period of the oscillation frequency fvco of an output clock signal. The frequency divider circuits 15a to 15i generate respective frequency divided output signals in 0.5 units, using clock signals of the four oscillation frequencies. FIG. 16 depicts a diagram showing a circuit configuration of a divide-by-1.5 frequency divider circuit disclosed in Patent Document 1. Referring to FIG. 16, the divide-by-1.5 frequency divider 15b includes a frequency divider 21, connected to the VCO 13 of the PLL circuit 14, a shift register 22 and a decoder 23. Clock signals CP1 to CP4, output from the VCO 13, are delivered as inputs to the divide-by-1.5 frequency divider 15b, and a 1.5-divided frequency division clock signal is delivered as an output. The frequency divider 21 includes two D-flip-flops DFF1 and DFF2, connected in cascade, and a NOR 1 that delivers a NOR output from the outputs of the d-flip-flops DFF1 and DFF2. A data terminal D of DFF1 receives an output of the NOR1 that receives data outputs Q of DFF1 and DFF2. An output signal of the frequency divider 21 is delivered from DFF 2. The shift register 22 includes four D-flip-flops DFF3 to DFF6 which receive the clock signals CP1 to CP4, respectively. The output of the frequency divider 21 is delivered to the initial stage D-flip-flop DFF 3 and output signals A to D are taken out from the outputs of the D-flip-flops DFF3 to DFF6, respectively. A NAND circuit NAND1 in the decoder 23 receives the signal A and a signal obtained by inverting the signal B by an inverter INV1. A NAND circuit NAND 2 receives the signal C and a signal obtained by inverting the signal D by an inverter INV 2. The 1.5-divided frequency division clock signal is taken out from a NAND circuit NAND 3 that receives output signals of the NAND circuits NAND1 and NAND2.
As a technique relevant to the frequency divider circuit, in which it is possible to switch between different integer frequency division numbers, Patent Document 2, for example, discloses a configuration in which the frequency division number may be selected from among 8, 9, 10, 16, 17 and 18 by control signals M1, M2 and M3. On the other hand, Patent Document 3 discloses a configuration of a multi-modulus p/p+1/p+2/p+4 prescaler that uses a p/p+1 dual modulus counter.
[Patent Document 1]
JP Patent Kokai Publication No. JP2004-56717A
[Patent Document 2]
JP Patent Kokai Publication No. JP2006-54806A
[Patent Document 3]
JP Patent Kokai Publication No. JP2003-124808A